Low power set associative cache memory
US5913223A · kind A · utility
32Cited by
5References
8Claims
0Family size
Inventors
Key dates
| Filing date | Jan 25, 1993 |
| Grant date | Jun 15, 1999 |
| Priority date | — |
| Expiry date | Jan 25, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A four-way cache data memory is provided, having a cache data RAM (30) and a tag RAM (28). The tag RAM (28) is enabled to access one of the tags therein. This tag is compared with the tag portion of the received memory address to determine if a tag is stored therein. If a true comparison results, a HIT is indicated and this is utilized to enable a portion of the cache data RAM (30). The data in the enabled portion is then output on the data bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.