DRAM applications using vertical MISFET devices
US5914504A · kind A · utility
33Cited by
6References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 17, 1996 |
| Grant date | Jun 22, 1999 |
| Priority date | — |
| Expiry date | Jun 17, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
Abstract
The present invention relates to RAM circuits comprising memory cells and logic circuitry wherein each of the memory cells comprise at least one Vertical MISFET device comprising a stack of several layers a source layer, a channel layer, a drain layer and a capacitor on the top of the stack of several layers of the Vertical MISFET device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.