Voltage generating circuit
US5914631A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 4, 1997 |
| Grant date | Jun 22, 1999 |
| Priority date | — |
| Expiry date | Aug 4, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F1/465
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A voltage controlled delay circuit is formed by m number of gates connected in series, phases of a clock signal and a delay signal are compared by a phase comparator, an up signal or a down signal is output, an integrated signal is generated by an integrator, a voltage signal following this is generated by a buffer and fed back as an operating power source voltage to the voltage controlled delay circuit, and further an internal power source voltage following the voltage signal is generated by a buffer and a pMOS transistor, therefore the internal power source voltage of the required lowest limit can be supplied in response to the frequency of the clock and a reduction of the voltage and conservation of the electric power of the LSI circuit can be achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.