Overvoltage-tolerant input-output buffers having a switch configured to isolate a pull up transistor from a voltage supply
US5914844A · kind A · utility
20Cited by
27References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 14, 1997 |
| Grant date | Jun 22, 1999 |
| Priority date | — |
| Expiry date | Oct 14, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The invention relates to a mixed voltage bus system and in particular, interfaces between a number of integrated circuits and a bus where some of the integrated circuits operate at one logic level and others operate at a different logic level. An overvoltage tolerant interface for a semiconductor integrated device particulary useful in such a system may contain a pad, a pull-up transistor coupled to the pad, a voltage supply having an operating voltage, and an isolation switch operative to isolate the pull-up transistor from the voltage supply when a voltage at the pad exceeds the operating voltage of the voltage supply.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.