Method and system for generating a mask layout of an optical integrated circuit
US5914889A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 1996 |
| Grant date | Jun 22, 1999 |
| Priority date | — |
| Expiry date | Sep 13, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02B2006/12173
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A computer system and method provide a CAD tool by which a mask for an application specific optical integrated circuit, chip, or wafer may be generated both easily and quickly. The method involves the step of receiving the design for an optical circuit with the circuit design including at least one optical component. Each optical component in the optical circuit is defined by one or more geometric shapes, such as a trapezoid, rectangle, or an arcuate polygon. The method further includes the step of retrieving parameters which define the manufacturing standard by which the optical circuit will be fabricated as well as parameters which define the optical components in the optical circuit. Based on the parameters and the geometric shapes, a plot is generated which forms a mask layout for the optical circuit. The mask layout can then be viewed by a graphical editor whereby a designer can receive visual confirmation that the mask layout accurately portrays the desired optical circuit, chip, or wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.