Fixed wireless loop system having dual direct synthesizer
US5914961A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 1997 |
| Grant date | Jun 22, 1999 |
| Priority date | — |
| Expiry date | Dec 10, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/7073
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Disclosed is apparatus including circuitry for providing synchronizing clocks to a transmitter and a receiver of a subscriber unit (SU) that communicates with a radio base unit (RBU) in a synchronous CDMA communication system. The apparatus includes an accumulator for generating a digital signal having a changing magnitude. The accumulator is initialized to a value of a phase command received from the RBU. The apparatus further includes a first circuit having an input coupled to an output of the accumulator for converting a content of the accumulator to a synchronized receiver clock signal, wherein the accumulator content is periodically adjusted to maintain the receiver clock signal in synchronism with a serial bit stream received from the RBU. In accordance with this invention the apparatus further includes a summer circuit having an input coupled to the output of the accumulator for combining the content of the accumulator, representing the commanded receiver side phase difference from RBU timing, with a value of a transmitter timing offset commanded by the RBU. The summer circuit provides a summation signal to a second circuit that converts the summation signal to a synchronize…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.