Digital signal error reduction apparatus
US5914983A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 6, 1995 |
| Grant date | Jun 22, 1999 |
| Priority date | — |
| Expiry date | Sep 6, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03662
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A digital signal error reduction apparatus of the present invention tracks and reduces both quickly changing errors and static errors in a digital signal which are caused by time variant multipath distortion, co-channel interference, and other transmission path interferences, including nonlinear distortion. A transversal filter is implemented for filtering the digital signal. A error detection device is implemented for calculating an error of the digital signal. A coefficient engine device is used for receiving the digital signal and the error, for extracting the error, and for updating a tap coefficient for the transversal filter so that the error is minimal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.