Patent · US Expired

Raised source/drain using recess etch of polysilicon

US5915183A · kind A · utility

47Cited by
12References
14Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJun 26, 1998
Grant dateJun 22, 1999
Priority date
Expiry dateJun 26, 2018

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D30/0212
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

A process for forming raised source/drain junctions using CMP (Chemical Mechanical Polishing) combined with a recess etch of blanket polysilicon. The raised source/drains are defined by gate conductors and by raised STI (Shallow Trench Isolation) which also reduces leakage current through the devices and improves the threshold voltage control. The process uses a salicide gate conductor, and uses conventional polysilicon deposition, CMP, and recess steps to form the raised source/drain junctions, such that it is readily implemented in commercially feasible manufacturing processes.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.