Compact ROM matrix

US5917224A · kind A · utility

Assignee

• Dolphin Integration · FR

Inventor

• Louis Zangara · Seyssinet-Pariset, FR

Key dates

• Filing date: Jun 2, 1997
• Grant date: Jun 29, 1999
• Expiry date: Jun 2, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B20/00

Abstract

A matrix memory array includes a P-type semiconductor substrate, thick oxide columns separating active columns, gate rows, a gate insulator interposed at the locations where these rows cover the active columns, N-type islands limited by the thick oxide columns and the gate rows, first conductive columns at the pitch of the active columns, constituting bit lines, second conductive columns at a pitch which is twice that of the first columns, constituting reference lines, and connections between each island and a first or second conductive column.