Area-efficient implication circuits for very dense Lukasiewicz logic arrays
US5917338A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 25, 1998 |
| Grant date | Jun 29, 1999 |
| Priority date | — |
| Expiry date | Mar 25, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A one-diode circuit for negated implication (.about..fwdarw.) is derived from a 12-transistor Lukasiewicz implication circuit (.fwdarw.). The derivation also yields an adjustable three-transistor implication circuit with maximum error less than 1% of full scale. Two Lukasiewicz logic arrays (.English Pound.LAs) are proposed that use area-efficient implementations of the one-diode and three-transistor implication circuits. The very dense diode-tower .English Pound.LA contains 36,000 implications in an area that previously held 92 implications; the three-transistor .English Pound.LA contains 1,990 implications. Both .English Pound.LAs double the number of inputs per pin on the IC package. Very dense .English Pound.LAs make .English Pound.LA-based fuzzy controllers and neural networks practical. As an example, an .English Pound.LA retina that detects edges in 15 nanoseconds is described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.