Three state phase detector
US5917356A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 1995 |
| Grant date | Jun 29, 1999 |
| Priority date | — |
| Expiry date | Sep 11, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/095
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase detector circuit receives both a reference clock signal and a sense clock signal and produces a synchronization signal if the sense and reference clock signals are in phase within a specified tolerance. A lead/lag signal is provided to a skew control circuit and accompanying delay circuits to increase or decrease the amount of delay on the reference clock signal and the sense clock signal if the two signals are not in phase within the specified tolerance. The sense clock signal is a feedback signal returned from logic circuitry, which originally receives the reference clock signal, which may be supplied by a master clock signal within a processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.