Method and apparatus for performing floating-point rounding operations for multiple precisions using incrementers
US5917741A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 29, 1996 |
| Grant date | Jun 29, 1999 |
| Priority date | — |
| Expiry date | Aug 29, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/49957
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit and method for rounding a number in one of a first or second format to produce a rounded result wherein the number is represented by a set of bits. A first incrementer increments a first subset of the set of bits in response to being enabled and a second incrementer coupled to the first incrementer increments a second subset of the set of bits in response to being enabled. Mode selection logic coupled to the first and second incrementers selectively enables one of the first or second incrementers in response to a control signal indicating the format of the number to be rounded, the first incrementer being enabled if the number is in the first format and the second incrementer being enabled if the number is in the second format.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.