Fault tolerant memory system
US5917838A · kind A · utility
26Cited by
2References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 5, 1998 |
| Grant date | Jun 29, 1999 |
| Priority date | — |
| Expiry date | Jan 5, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fault tolerant memory system having a triple bit error correction and quadruple bit error detection capability is disclosed using control logic coupled to multiple decoders each having single bit error correction/double bit error detection capabilities. The memory system can also be provided with a sparing system which provides an additional memory device to circumvent failures in individual memory devices. The memory system is suited for severe environments such as computing systems operating in outer space.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.