Method for processor modeling in code generation and instruction set simulation
US5918035A · kind A · utility
57Cited by
4References
45Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 15, 1995 |
| Grant date | Jun 29, 1999 |
| Priority date | — |
| Expiry date | May 15, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of modeling a programmable processor is particularly adapted for use in an automatic retargetable code generator and instruction set simulator. The method represents the processor as a single graph with vertices and edges. The graph includes the instruction set of the processor and includes information about the hardware of the processor. The graph is linked to tools and libraries required to program and simulate the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.