Data processing system having an input/output coprocessor with a separate visibility bus
US5918064A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 1997 |
| Grant date | Jun 29, 1999 |
| Priority date | — |
| Expiry date | Feb 18, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/124
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system includes a central processing unit (CPU) (20), a peripheral bus (32), and an input/output (I/O) coprocessor (38). The CPU (20) and the I/O coprocessor (38) are coupled to the peripheral bus (32). The I/O coprocessor (38) has a plurality of front-end channels (50) for receiving a time-base, and in response, for providing a time-base reference for input signals and generating output signals using the time-base reference. A back-end processor (80) controls operation of the plurality of front-end channels (50) in response to executing instructions. A visibility bus (40), coupled to the back-end processor (80), is for providing visibility of the internal registers of the back-end processor (80) independent of the CPU (20). The visibility is provided for development of the instructions executed by the back-end processor (80).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.