System architecture for and method of dual path data processing and management of packets and/or cells and the like
US5918074A · kind A · utility
137Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 25, 1997 |
| Grant date | Jun 29, 1999 |
| Priority date | — |
| Expiry date | Jul 25, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5681
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A novel networking architecture and technique for reducing system latency caused, at least in part, by access contention for usage of common bus and memory facilities, wherein a separate data processing and queue management forwarding engine and queue manager are provided for each I/O module to process packet/cell control information and delivers queuing along a separate path that eliminates contention with other resources and is separate from the transfer of packet/cell data into and from the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.