Methods for forming integrated circuit capacitors including dual electrode depositions
US5918135A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 1997 |
| Grant date | Jun 29, 1999 |
| Priority date | — |
| Expiry date | Jun 2, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/692
Abstract
A method for forming an integrated circuit device includes the steps of forming a first capacitor electrode on a substrate and forming a first wiring electrode on the substrate. An insulating layer is formed on the first capacitor electrode and on the first wiring electrode opposite the substrate. A second capacitor electrode is formed on a portion of the insulating layer opposite the first capacitor electrode. A contact hole is formed in the insulating layer exposing a portion of the first wiring electrode. A second wiring electrode is then formed on the exposed portion of the wiring electrode, after forming the second capacitor electrode. Related structures are also discussed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.