Method of fabricating package for housing semiconductor element
US5918796A · kind A · utility
5Cited by
7References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 14, 1997 |
| Grant date | Jul 6, 1999 |
| Priority date | — |
| Expiry date | Feb 14, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a package for housing a semiconductor element, comprising applying solder paste within plural depressions which are formed on at least one principal surface of an insulating substrate and have electrical connection pads, protruding the surface of the solder paste from the principal surface of the insulating substrate, mounting solder balls on the surface of the solder paste, and fusing the solder paste and the solder balls to produce unitary structures in order to form connection terminals with spherical protrusions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.