Method and apparatus for processing an interrupt
US5919255A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 1997 |
| Grant date | Jul 6, 1999 |
| Priority date | — |
| Expiry date | Mar 12, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4812
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention provides a method for interrupting processing by a processor. The method includes the step of requesting an analysis interrupt by setting a bit in a register in the processor (119), the bit associated with an analysis interrupt, the analysis interrupt having a configurable priority. The method also includes the step of detecting the analysis interrupt request. The method further comprises assigning an assigned priority level (114) to the analysis interrupt from a range of priority levels and processing the analysis interrupt (124) based on the assigned priority level. The invention also provides a processor having a memory unit (14, 16) and a central processing unit (12) operable to access the memory unit. The central processing unit (12) includes an interrupt priority parameter storage system (80) for storing an interrupt priority parameter. The central processing unit further includes a configurable interrupt detection system (36) operable in combination with the central processing unit to detect a configurable interrupt. The central processing unit also includes an interrupt handling system (38) operable in combination with the central processing unit to process a …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.