Apparatus and method for fault tolerant operation of a multiprocessor data processing system
US5919266A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 1993 |
| Grant date | Jul 6, 1999 |
| Priority date | — |
| Expiry date | Apr 2, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2023
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fault tolerant multiple processor data processing system is described. The system includes a number of processors linked together in a network. One processor is designated the master processor and coordinates the operation of all of the processors. The network is coupled to a number of memory devices which store information which is utilized by the processors. The apparatus includes a redundant mechanism for identifying a failure of a processor. If the master processor fails, a new master processor is selected, in a dynamic manner, from the remaining operative processors. The selection of a new master processor is based upon a contention operation in which the operative processors contend to become the new master processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.