Switched magnetic field sensitive field effect transistor device
US5920090A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 13, 1998 |
| Grant date | Jul 6, 1999 |
| Priority date | — |
| Expiry date | Feb 13, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D48/40
Abstract
The invention concerns a Switched MAGFET (MAGnetic field sensitive Field Effect Transistor). A preferred SMAGFET embodiment consists of a MAGFET structure with two equal sized drain contacts (3, 4), a gate area consisting of two equal sized and electrically isolated gate regions G1 and G2 (5, 6) separated by a third isolated gate region Gc (7) placed along the symmetry line of the device and slightly overlapping G1 and G2. The SMAGFET has a common source (1). By varying the gate voltage on Gc (with reference to the common source contact), the magnetic sensitivity of the SMAGFET may be controlled. By applying a first voltage on Gc, exchange of carriers from the channels beneath G1 and G2 is blocked. In case of an applied magnetic field, this will prevent Lorentz deflected carriers to cross symmetry line and redistribute the drain currents, i.e. the magnetic field sensitivity is virtually zero as the drain currents will remain unaffected by the magnetic induction. By changing the voltage at Gc to a second level, exchange of carriers from channels beneath G1 and G2 may take place. In case of an applied magnetic field, this will allow Lorentz deflected carriers to cross symmetry line a…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.