Fully digital clock synthesizer
US5920211A · kind A · utility
11Cited by
5References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 27, 1997 |
| Grant date | Jul 6, 1999 |
| Priority date | — |
| Expiry date | Mar 27, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/00006
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A fully digital clock multiplier capable of generating any N/M multiple of an input clock frequency with a precise duty cycle is provided. The input clock signal is divided by M to create a divided clock signal. The propagation of the input clock signal along a delay cell string during a half cycle of the divided clock signal is then measured. The measured propagation is then scaled by a factor N to select an appropriate delay cell string length within a ring oscillator for generating an output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.