Method and apparatus for generating an eight-to-fourteen modulation data restoring clock signal
US5920214A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 1997 |
| Grant date | Jul 6, 1999 |
| Priority date | — |
| Expiry date | Mar 11, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/087
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and phase locked loop for generating an eight-to-fourteen (EFM) data restoring clock signal. A frequency detector detects the number of clock pulses input during a pulse width of the EFM data signal, compares the detected number with predetermined maximum and minimum values, and outputs a signal indicative of the resulting comparison value. A voltage controlled oscillator varies an oscillating frequency in response to a DC control signal and outputs the clock pulses corresponding to the oscillating frequency. A programmable counter frequency-divides the clock pulses generated by the voltage controlled oscillator in response to a predetermined speed multiple and outputs the frequency-divided clock pulses. A phase detector detects a phase difference between the EFM data signal and the clock pulses generated by the programmable counter and outputs a signal indicative of the phase difference. A mixer mixes the output of the phase detector with the output of the frequency detector. A control signal generator outputs the DC control signal according to the output of the mixer. Thus, the data access speed is increased and the phase locked loop is more rapidly set into a locking ra…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.