Method for generating a reduced order model of an electronic circuit
US5920484A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 2, 1996 |
| Grant date | Jul 6, 1999 |
| Priority date | — |
| Expiry date | Dec 2, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for model reduction (48) for electronic circuit simulation (52) of an electronic circuit using multipoint matrix Pade approximation is provided herein. Using the method, state equations are generated from a linear circuit to be analyzed. One or more expansion frequencies and a number of moments for each of the one or more expansion frequencies are provided. Starting block Lanczos vectors using a first expansion frequency of the one or more expansion frequencies and the state equations are generated. New block Lanczos vectors are generated from the starting block Lanczos vectors. The new block Lanczos vectors are scaled and normalized. Breakdowns in the new block Lanczos vectors are detected and treated to generate new starting block Lanczos vectors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.