Nonvolatile semiconductor memory device
US5920507A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 1997 |
| Grant date | Jul 6, 1999 |
| Priority date | — |
| Expiry date | Nov 12, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile semiconductor memory device comprising a memory cell array having a plurality of electrically writable memory cells arranged in a matrix form, each of the memory cells having three or more logic states so as to store a multi-value data "i" (i=0, 1, . . . , n-1: n.gtoreq.3), a plurality of data latch circuits for temporarily storing data controlling a write state of the plurality of memory cells of the memory array, write verify circuit for confirming the write state of the plurality of memory cells, and an "i" data batch verify circuit for batch-detecting whether or not the memory cell where data "i" should be written reaches a memory state of data "i."
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.