Method of forming a semiconductor device having dual inlaid structure
US5920790A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 1997 |
| Grant date | Jul 6, 1999 |
| Priority date | — |
| Expiry date | Aug 29, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming semiconductor device (1) that includes providing a substrate (10) having a metal interconnect (12), depositing a via interlevel dielectric (ILD) layer (20) over the substrate (10) and the metal interconnect (12), etching the via ILD layer (20) to form a via (30) over the metal interconnect (12), depositing a trench ILD layer (32) over the via ILD layer (12) and the via (30), etching the trench ILD layer (32) to form a trench (40), the trench (40) being contiguous with the via (12), and depositing a metal (44) so as to fill the via (30) and the trench (40), and provide electrical connection with the metal interconnect (12).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.