Method and system for inhibiting transfer of duplicate write addresses in multi-domain processor systems with cross-bus architecture to reduce cross-invalidation requests
US5920892A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 26, 1996 |
| Grant date | Jul 6, 1999 |
| Priority date | — |
| Expiry date | Aug 26, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A two domain digital network with each domain having its own system bus and its own bus exchange module permits Write operation addresses to be passed between domains. Each bus exchange module provides a match filter which prevents the passage from one bus to the other bus of a duplicate Write operation (OP) address which has already been transferred, thus relieving the busses of excess traffic when a duplicate Write OP address is being sent to a cache memory for an invalidation operation. A Read operation will nullify the match filter to then allow passage of each incoming Write OP invalidation address to the snoop invalidation queue, but prevent the passage of a subsequent duplicate Write OP address, so long as the read OP is ongoing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.