Patternless technique for building self-aligned floating gates

US5922619A · kind A · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventor

• David Leonard Larkin · Richardson, US

Key dates

• Filing date: Oct 2, 1997
• Grant date: Jul 13, 1999
• Expiry date: Oct 2, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0411

Abstract

A patternless, self-aligning method of forming a floating gate on a silicon wafer having a plurality of raised field oxide isolation structures. The method of the present invention includes depositing a polysilicon layer onto the silicon wafer and the raised field oxide isolation structures, depositing a polysilicon etch masking layer onto the polysilicon layer, and planarizing the polysilicon etch masking layer. The polysilicon etch masking layer is then etched to expose the polysilicon layer over the raised field oxide isolation structures. The exposed polysilicon layer is then etched to remove the polysilicon layer over the raised field oxide isolation structures. The remaining polysilicon etch masking layer is then removed, leaving a plurality of polysilicon regions covering the silicon wafer between the field oxide isolation structures.