Clock signal distribution circuit of tree structure with minimized skew
US5923188A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 1996 |
| Grant date | Jul 13, 1999 |
| Priority date | — |
| Expiry date | Jun 12, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Letting p be a definite integer, q be a varying integer from 1 to p, r be an arbitrary integer such that 1.ltoreq.r.ltoreq.p, and s be a varying integer from 2 to 2p+1, among a total of 2p+1 fan-like stages each having fan-out outputs thereof equalized to each other in load and number of associated fan-like stages, a respective 2q-th one comprises branch circuits each composed of one of a pair of logic gates, a 2r+1-th one comprises branch circuits each composed of a multi-input logic gate, a respective 2q-1-th one excepting the 2r+1-th one comprises branch circuits of which any one is composed of the other of the pair of logic gates, and a respective s-th one comprises branch circuits each respectively arranged within a cell layout region therefor and connected to an s+1-th stage at a vicinal location to a barycenter of the cell layout region to repeat a fan-out output of an s-1-th fan-like stage, as it is a clock signal distributed thereto.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.