Method and apparatus for transferring signals between multiple clock timing domains
US5923193A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 1996 |
| Grant date | Jul 13, 1999 |
| Priority date | — |
| Expiry date | Dec 11, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0012
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Briefly, in accordance with one embodiment, an integrated circuit includes: electronic circuitry for transferring digital data signals along a digital data signal path between different clock timing domains. The clock timing domains have a common higher frequency source clock. A first clock timing domain clock signal has a relatively fixed phase and a second clock timing domain clock signal has a relatively varying phase. The electronic circuitry includes delay elements in clock signal paths associated with the digital data signal path so that along the digital data signal path, clock signals in different clock timing domains are respectively staggered for a relatively short time compared with a given cycle of the source clock. The electronic circuitry further includes a digital data signal path including a data value retention element to delay the transfer of digital data signals between different clock timing domains at selected times.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.