Charge injection cancellation technique
US5923206A · kind A · utility
8Cited by
10References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 27, 1997 |
| Grant date | Jul 13, 1999 |
| Priority date | — |
| Expiry date | Mar 27, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/005
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An MOS FET circuit with a summing circuit at the input of an amplifier to provide charge cancellation. The summing circuit is capacitively coupled to the input with a charge cancellation capacitor. A separate amplifier, having components substantially the same as the components of the first amplifier, is connected through the charge cancellation capacitor to the first amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.