Processing system with single-buffered display capture
US5923385A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 1996 |
| Grant date | Jul 13, 1999 |
| Priority date | — |
| Expiry date | Oct 11, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N9/641
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for single-buffered display capture which eliminates a "tearing" problem inherent in certain conventional video display techniques. A video signal including a sequence of frames each having an even field and an odd field is applied to a video capture circuit. First and second sets of lines each representing a different subset of all the lines in a given even or odd field are captured in the video capture circuit and displayed by a video display circuit. The video capture circuit captures the first set of lines in an even field of the video signal during a time period in which the video display circuit displays the second set of lines in the even field. The video capture circuit also captures the second set of lines in an odd field of the video signal during a time period in which the video display circuit displays the first set of lines in the odd field. The video capture circuit utilizes an odd-numbered decimation factor to determine the first and second sets of lines from among all lines in the even and odd fields.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.