Method for controlling a semiconductor manufacturing process by failure analysis feedback
US5923553A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 5, 1996 |
| Grant date | Jul 13, 1999 |
| Priority date | — |
| Expiry date | Oct 5, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A method for controlling a semiconductor manufacturing process by failure analysis feedback compares a previous failure analysis result with current real-time process conditions. The method uses the steps of: a) establishing a monitoring data base with abnormal process condition data, the abnormal process condition data being obtained by a correlation between a yield for each manufactured lot and corresponding process conditions for semiconductor equipment when the yield is lowered or semiconductor equipment malfunctions have occurred; b) establishing an equipment data base by obtaining real-time process conditions for on-line semiconductor equipment; c) comparing the real-time process conditions for the on-line semiconductor equipment with the abnormal process conditions of the monitoring data base; and d) stopping the operation of the on-line semiconductor equipment when differences between the real-time and abnormal process conditions fall below a predetermined level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.