Variable density fill shape generation
US5923563A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 1996 |
| Grant date | Jul 13, 1999 |
| Priority date | — |
| Expiry date | Dec 20, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is directed to a method for adding fill shapes to a chip in a manner which accommodates a wide range of within-chip pattern density variations and provides a tight pattern density control (i) within a chip and (ii) from chip to chip. The present invention imposes a grid over a chip design pattern, wherein each section of the grid contains a portion of the chip design. A pattern density is then determined for each section of the grid, based on that portion of the chip design pattern which lies within the particular grid section. The results of the pattern density determination are used to determine where to place fill shapes in the chip design in order to increase a density value in each section of the grid to that of a target density value. The method and apparatus of the present invention provide a best fit approximation to the desired pattern density consistent with a set of layout rules for the level being patterned.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.