Method for eletronically representing a number, adder circuit and computer system
US5923575A · kind A · utility
6Cited by
4References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 15, 1997 |
| Grant date | Jul 13, 1999 |
| Priority date | — |
| Expiry date | Aug 15, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/38
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to a method for electronically representing a number V in a binary data word. Both the exponent and the mantissa are represented as 2' complement. The mantissa is normalized to 0.1.F if the number V is positive where F is the fraction of the mantissa. In case that the number V is negative the fraction F is normalized to 10.F. Usage of this format allows to design an improved adder which requires less hardware.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.