SRAM with ROM functionality
US5923582A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 3, 1997 |
| Grant date | Jul 13, 1999 |
| Priority date | — |
| Expiry date | Jun 3, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device including a first block of random access memory (RAM) cells having preprogrammed states, a second block of random access memory cells, and a select circuit configured to reset the first block of RAM cells to their preprogrammed states. When the first block of memory cells are reset to their preprogrammed states, the first block of memory cells may function as ROM memory cells that may be accessed at RAM speeds. The first block of RAM cells may not require additional nonvolatile circuitry in order to perform the ROM function; rather, the first block of RAM cells may each be configured to operate as both a volatile and nonvolatile memory cell using the same cell structure. For one embodiment, the select circuit alters the power applied to the first block of RAM cells to cause these RAM cells to perform a ROM function. Since, the first block of RAM cells may store RAM data when the device operates in RAM mode, and may store preprogrammed ROM data when reset by the select circuit, the first block of RAM cells may have a storage capacity that is greater than the number of RAM cells in the first block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.