Multi-port DRAM cell and memory system using same
US5923593A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 1996 |
| Grant date | Jul 13, 1999 |
| Priority date | — |
| Expiry date | Dec 17, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-port DRAM cell structure that enables read, write and refresh accesses at each port of the DRAM cell. The DRAM cell includes a storage capacitor for storing a data value, and a plurality of ports for accessing the storage capacitor. Each port enables both read and write accesses to the storage capacitor. Each port can include a port access transistor, a port bitline and a port wordline. The port access transistor includes a gate electrode, a source and a drain. The source of the port access transistor is coupled to the storage capacitor, the drain of the port access transistor is coupled to the port bitline, and the gate electrode of the port access transistor is coupled to the port wordline. This cell architecture enables overlapping read and write accesses to be simultaneously performed at the various ports of the multi-port DRAM cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.