Space-efficient semiconductor memory having hierarchical column select line architecture

US5923605A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Gerhard Mueller · Meitingen, DE
• Heinz Hoenigschmid · Starnberg, DE

Key dates

• Filing date: Sep 29, 1997
• Grant date: Jul 13, 1999
• Expiry date: Sep 29, 2017

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C11/4087
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Disclosed is a multiple bank semiconductor memory (40) (e.g., DRAM) capable of overlapping write/read operation to/from memory cells of different banks (MAa, MAb), and having a space efficient layout. Chip size is kept small by employing a single column decoder (44) for different banks, and a hierarchical column select line architecture, with bit line switches (59, 61, 63, 65) of different columns having a shared active area such as a common source region. In an illustrative embodiment, global column select lines (GCSL.sub.1 -GCSL.sub.(N/K)) selectively activate global bit line switches (67, 68) which are coupled to bank-specific data lines (LDQ, LDQ). Several bank bit line switches (59-66) are coupled to each global bit line switch, with two or more bank bit line switches of different columns having a shared diffusion region to realize a compact layout.