Synchronous pipelined burst memory and method for operating same
US5923615A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 1998 |
| Grant date | Jul 13, 1999 |
| Priority date | — |
| Expiry date | Apr 17, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1039
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A synchronous pipelined burst memory (20) achieves high speed by violating conventional pipelining rules. The memory (20) includes an address register (24) which latches a burst address during a first cycle of a periodic clock signal. The burst address is driven to an input of an asynchronous memory core (40), but output data from the asynchronous memory core (40) is not latched until a third cycle of the periodic clock signal which occurs after a second cycle of the periodic clock signal which is immediately subsequent to the first cycle. The memory (20) outputs successive data elements of the burst during consecutive cycles of the periodic clock signal to complete the burst cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.