Error correction in a digital transmission system
US5923680A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 1997 |
| Grant date | Jul 13, 1999 |
| Priority date | — |
| Expiry date | Jun 5, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5673
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Random bit errors in a digital transmission system in which data is scrambled and subsequently descrambled are detected by parsing the descrambled data into words, determining a syndrome error word for each data word, and determining a parity error word for each data word. A data word is left uncorrected when its corresponding syndrome error and parity error words are both zero. Single bit error correction of a data word is effected when its corresponding syndrome error and parity error words are both non-zero. Double or multiple bit error correction of a data word is effected when its corresponding parity error word is zero and its corresponding syndrome error word is non-zero.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.