Parallel synchronous header correction machine for ATM
US5923681A · kind A · utility
5Cited by
19References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 24, 1998 |
| Grant date | Jul 13, 1999 |
| Priority date | — |
| Expiry date | Feb 24, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S370/905
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An error correction circuit for an ATM header of an ATM cell uses a sequence of synchronous comparator circuits to generate a correction mask. The sequence of comparators, when used in a processor having a 32-bit bus, provide for near minimum processing delay at an ATM node. The error correction circuit also provides error status flags for an ATM cell processor, allowing for the processor to discard ATM cells with multiple errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.