Non-interrupting power control for fault tolerant computer systems
US5923830A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 7, 1997 |
| Grant date | Jul 13, 1999 |
| Priority date | — |
| Expiry date | May 7, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2043
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-intrusive power control for a fault tolerant computer system which uses redundant voting at the hardware clock level. The computer includes three or more commercial central processing units (CPUs) operating synchronously. Outputs to system memory and system bus are voted by a radiation tolerant gate array which may be implemented in a custom integrated circuit. An interface control coupled to the voter can remove or connect power from a CPU and adjust CPU inputs, preventing damage to the components without terminating an operating program. The inputs and outputs at each write to and read from system memory are voted at each CPU clock cycle. A vote status and control circuit "reads" the status of the vote and controls the state of the CPUs using hardware and software. The system logic selects the best chance of recovering from a detected fault by re-synchronizing all CPUs, powering down a faulty CPU, or switching to a spare computer, resetting and re-booting the substituted CPU.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.