Split-SMP computer system configured to operate in a protected mode having repeater which inhibits transaction to local address partiton
US5923847A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 1996 |
| Grant date | Jul 13, 1999 |
| Priority date | — |
| Expiry date | Jul 2, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/173
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system includes multiple local buses to which processors and other devices may be connected. A repeater is coupled to each of the local buses. Additionally, a top level repeater is coupled to each of the repeaters. The repeaters transmit transactions from the corresponding local buses to the top repeater. The top repeater, based upon the local or global nature of the transaction, transmits the transaction to one or more of the repeaters. The repeaters receiving the transaction then transmit the transaction upon the local buses attached thereto. If the transaction is a local transaction, the top repeater transmits the transaction to those repeaters which are configured into a local domain with the repeater which detected the initial transaction. The local domain comprises one or more repeaters which are logically interconnected. The local buses attached thereto logically form one SMP bus to which devices may be attached. Alternatively, the transaction may be a global transaction. The top repeater transmits the global transaction to all repeaters in the system. Subsequently, the transaction is retransmitted upon all of the local buses. In one embodiment, a transaction is d…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.