Hierarchical memory architecture for a programmable integrated circuit having an interconnect structure connected in a tree configuration
US5924115A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 1996 |
| Grant date | Jul 13, 1999 |
| Priority date | — |
| Expiry date | Mar 29, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hierarchical memory for use in a programmable gate array integrated circuit comprises an interconnect structure having a plurality of interconnect nodes electrically connected in a tree configuration. The interconnect nodes include a root node which receives a multi-bit address word indicative of a selected memory location. The hierarchical memory further includes a plurality of memory cells electrically connected to the interconnect structure to form leaf nodes of the tree. Each of the memory cells contains at least one memory location for storing binary data. The interconnect structure is traversed from the root node to a memory cell containing the selected memory location based upon the multi-bit address word, wherein the interconnect structure provides a communication path for accessing the selected memory location from the root node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.