Clock rate compensation for a low frequency slave device
US5925135A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 1996 |
| Grant date | Jul 20, 1999 |
| Priority date | — |
| Expiry date | Sep 26, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A slave device having clock rate compensation circuitry for low frequency operation. The slave device is coupled to a bus having a first operating frequency yet uses a slave clock signal having a frequency less than the first operating frequency. The slave device includes a bus clock driver circuit coupled to a bus clock interface for a bus clock signal. A slave controller state machine is clocked by the slave clock signal and accordingly operates at less than the first operating frequency. The clock rate compensation circuitry receives the bus clock signal, a data signal, and the slave clock signal, and synchronizes bus events for the state machine. The clock rate compensation circuitry also asynchronously begins a bus clock signal stretching period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.