Apparatus and method for error free loading of a programmable non-volatile memory over a datalink
US5925140A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 23, 1997 |
| Grant date | Jul 20, 1999 |
| Priority date | — |
| Expiry date | Jul 23, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/16
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for error free loading of a programmable non-volatile memory device over a serial or parallel data link. The apparatus comprises a host system connected to a unit to be programmed via a data communications link. The host system comprises a central processing unit (CPU) coupled to random access memory (RAM) via a bus, and the unit to be programmed represents a device in which a programmable non-volatile memory is installed. The data to be stored in the programmable non-volatile memory is sent by the host system in data packets to allow error checking to be applied to each block transmitted across the data communications link to the unit to be programmed. The host system builds data blocks in frames, computes an error detection code, and sends the frames containing the data and the error detection code across the data link to the unit to be programmed. The unit to be programmed uses the error detection code to determine if the transmission was successful. If the transfer was error free, the data is loaded into the programmable non-volatile memory in the unit to be programmed. If the frame was received in error, the unit to be programmed sends a frame back to t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.