Semiconductor device having interconnect lines and connection electrodes formed in groove portions of an insulating layer
US5925931A · kind A · utility
234Cited by
8References
13Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 22, 1997 |
| Grant date | Jul 20, 1999 |
| Priority date | — |
| Expiry date | Oct 22, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/12042
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor chip has such a structure as to have first connection electrodes formed at its upper circumferential edge portion and each exposed over a corresponding opening in a protective layer. An insulating layer is formed on the semiconductor chip except at each opening in the protective layer. Interconnect lines of an electroless-plated layer are formed on the first connection electrode. Solder bumps are formed on second connection electrodes formed together with the interconnect lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.