High speed digital bus termination
US5926031A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 1996 |
| Grant date | Jul 20, 1999 |
| Priority date | — |
| Expiry date | Oct 29, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0298
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Novel methods and apparatuses for terminating busses are disclosed based upon the number of devices secured to the bus. The impedance of the bus lines varies with the number of devices coupled to the bus. The number of devices coupled to the bus line is determined and a precision resistor is selected based upon the number of devices coupled to the bus matching the expected impedance of the bus. A voltage is generated across the precision resistor with a known current and that voltage is compared with the voltage generated across a controllable resistances such as a FET biased in the linear mode with a like current passing through the fed. A feedback network provides a control voltage to the control electrode of the FET to control the resistance of the FET so that the resistance of the FET equals the selected precision resistance. The same control voltage is coupled to the control electrode of other controllable resistances such as FETs operating in the linear region with each FET terminating a separate signal line. Hence, each FET has a resistance about equal to the resistance of each of the signal lines at the predetermined impedance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.