Selectable clock generation mode
US5926053A · kind A · utility
51Cited by
13References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 15, 1995 |
| Grant date | Jul 20, 1999 |
| Priority date | — |
| Expiry date | Dec 15, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing system includes circuitry and methodology for selecting clock generation modes between phase-locked loop and static delay line loop circuitries. The node may be selectable through an externally accessible pin, an internal bond wire option, a boundary test scan control point, or other programmable register or control point.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.