Self calibration circuitry and algorithm for multipass analog to digital converter interstage gain correction
US5926123A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 1997 |
| Grant date | Jul 20, 1999 |
| Priority date | — |
| Expiry date | Dec 8, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/144
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Autocalibration circuitry and an algorithm (method) for aligning interstage gain within a high resolution multipass analog-to-digital converter. The interstage gain alignment technique maximizes the signal-to-noise ratio and spurious free dynamic range of the multipass analog-to-digital converter. The multipass analog-to-digital converter uses an m-bit course analog-to-digital converter and an n-bit fine analog-to-digital converter whose input is derived from an m-bit digital-to-analog converter. Output words of the course and fine analog-to-digital converters are combined to produce an output word of the multipass analog-to-digital converter. The present invention applies a random signal into the m-bit digital-to-analog converter. The digital output of the n-bit fine analog-to-digital converter is statistically examined to discern the gain misalignment error. The sign of the gain misalignment error is correlated with the sign of the random signal applied to the m-bit digital-to-analog converter to null the gain error independently of the input signal sampled by the multipass analog-to-digital converter and without interrupting the conversion process of the multipass analog-to-digi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.